1. Field of the Invention
This invention relates generally to timing verification of semiconductor integrated circuits. More specifically, it relates to timing verification capable of statistical processing of variations in semiconductor integrated circuits.
2. Description of the Related Art
The static timing analysis (STA) has conventionally been utilized for timing verification of a logical circuit composed of semiconductor integrated circuits, etc. More specifically, based on delays, respectively, assigned to elemental devices forming a circuit, timing verification of the operation of the circuit is conducted by means of such a static timing analysis (STA) method. Without necessity to prepare test patterns, verification is conducted by cumulation of delays of the respective elemental devices, etc. in a signal transmission path.
Generally, elemental devices in a semiconductor integrated circuit vary in characteristics, in other words it is required that such variations be taken into consideration when conducting a static timing analysis (STA). More specifically, delays of the elemental devices are each multiplied by the same coefficient for representation of a respective variation for each elemental device, and a static timing analysis (STA) is executed in order to verify whether it is possible or not for the semiconductor integrated circuit to operate properly against in-chip variations (for related information, see Japanese unexamined patent publication No. 2002-222232).
More specifically, if, when the manufacturing process is set to such a condition that (i) the circuit operates at low speed, (ii) the chip temperature is high and, in addition, (iii) the power supply voltage is low, this is defined as a worst condition. On the other hand, if, when the manufacturing process is set to such a condition that (i) the circuit operates at high speed, (ii) the chip temperature is low and, in addition, (iii) the power supply voltage is high, this is defined as a best condition. For each of the worst and best conditions, the setup time and hold time of an internal circuit are verified.